SystemVerilog probes · 14Vivado: supported

typed parameters, one depending on another, localparam, #(.W(8),.K(3)) and positional #(4)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Overriding module parameters: Supported'

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/14_params.

design.sv

module adder #(parameter int W = 4, parameter logic [W-1:0] K = '0)
             (input logic [W-1:0] a, output logic [W-1:0] y);
  localparam int W2 = W * 2;
  logic [W2-1:0] wide;
  assign wide = a + K;
  assign y = wide[W-1:0];
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  localparam logic [3:0] C = 4'd9;
  adder #(.W(8), .K(8'd3)) u0 (.a(sw[7:0]),  .y(led[7:0]));
  adder #(4)               u1 (.a(sw[11:8]), .y(led[11:8]));
  assign led[15:12] = C;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h0510; #1
    if (!(led === 16'h9513)) begin $display("FAIL: #() overrides (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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