SystemVerilog probes · 16cVivado: supported

while loop in an always block (UG901 example)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 'Using While Loops' (p.257): 'When using always blocks, use while loops to execute repetitive procedures.'; 'Example of While Loop' (p.258) is this design's always block, while (!found && (i < P))

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 4 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048560 output bits compared, all equal'

What is the probe's code?

From test/sv/16c_while_loop.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  parameter P = 4;
  always @(sw) begin : find_first_zero        // UG901's while-loop example, as printed there
    integer i; reg found;
    led = '0; i = 0; found = 0;
    while (!found && (i < P)) begin
      found = !sw[i];
      led[i] = !sw[i];
      i = i + 1;
    end
  end
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  reg [15:0] want;
  integer i, k;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 32; i = i + 1) begin
      sw = {11'h5A3, i[4:0]}; #1
      want = 16'd0;                              // one-hot: the lowest zero among sw[3:0], none if all ones
      for (k = 3; k >= 0; k = k - 1) if (!sw[k]) want = 16'd1 << k;
      if (!(led === want)) begin $display("FAIL: first zero (sw=%h led=%h want=%h)", sw, led, want); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

previous: 'return expr;' inside a function
next: $clog2 in a localparam and a range, $bits, size cast 4'(expr)