SystemVerilog probes · 17Vivado: supported

$clog2 in a localparam and a range, $bits, size cast 4'(expr)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 21 (p.240): '$clog2: Supported, This is supported with SystemVerilog only', '$bits: Supported'; UG901 v2023.2 Ch.10 Table 27 (p.285): 'Cast operator: Supported'

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/17_clog2_bits_cast.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  localparam int DEPTH = 10;
  localparam int AW = $clog2(DEPTH);
  logic [$clog2(16)-1:0] idx;
  logic [11:0] word;
  assign idx  = sw[3:0];
  assign word = {sw[7:0], idx};
  assign led[4:0]   = $bits(word);
  assign led[7:5]   = AW[2:0];
  assign led[11:8]  = 4'(sw[15:8] + 8'd1) >> 1;   // the cast cuts the sum to 4 bits before the shift
  assign led[15:12] = $bits(idx);
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  reg [8:0] sum;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {i[7:0], 8'h5A}; #1
      sum = sw[15:8] + 1;
      // $bits(word) = 12, $clog2(10) = 4, 4'(sum) >> 1 = sum[3:1], $bits(idx) = 4
      if (!(led === {4'd4, 1'b0, sum[3:1], 3'd4, 5'd12})) begin $display("FAIL: $bits, $clog2 or the 4'() cast (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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