SystemVerilog probes · 18Vivado: supported

unique case / priority casez

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.287): 'unique-case, unique0-case, and priority-case: Supported'; Ch.10 (p.279): 'Vivado synthesis treats those as parallel_case and full_case'. UG901 v2022.2 Table 8-1 (p.290) said Not Supported

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/18_unique_priority.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  always_comb begin
    unique case (sw[1:0])
      2'd0: led[3:0] = 4'h1;
      2'd1: led[3:0] = 4'h2;
      2'd2: led[3:0] = 4'h4;
      2'd3: led[3:0] = 4'h8;
    endcase
    priority casez (sw[7:4])
      4'b1???: led[5:4] = 2'd3;
      4'b01??: led[5:4] = 2'd2;
      4'b001?: led[5:4] = 2'd1;
      default: led[5:4] = 2'd0;
    endcase
    led[15:6] = '0;
  end
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  reg [1:0] pri;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {8'hC3, i[7:0]}; #1
      pri = sw[7] ? 2'd3 : sw[6] ? 2'd2 : sw[5] ? 2'd1 : 2'd0;     // priority casez: the first matching item wins
      if (!(led === {10'd0, pri, 4'd1 << sw[1:0]})) begin $display("FAIL: unique case / priority casez (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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