SystemVerilog probes · 33bVivado: supported

inout pin only read (never assigned 'z) + one bidirectional pin

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. As 33: UG901 v2023.2 Ch.5 'Tristates' (p.86); UG953 v2022.2 Ch.5 IOBUF (p.386): 'Inference: Recommended'

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/33b_inout_read_only.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led, inout wire [7:0] JA);
  assign JA[0] = sw[0] ? sw[1] : 1'bz;   // JA[0] bidirectional
  assign led[0] = JA[0];
  assign led[1] = JA[1];                 // JA[1] only read, never assigned (no 'z' written)
  assign led[15:2] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  wire [7:0] JA; reg oe0 = 1'b0, d0 = 1'b0, oe1 = 1'b0, d1 = 1'b0;
  assign JA[0] = oe0 ? d0 : 1'bz;
  assign JA[1] = oe1 ? d1 : 1'bz;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led), .JA(JA));
  initial begin
    sw = 16'h0003; #1
    if (led[0] !== 1'b1) begin $display("FAIL: design drives JA[0]=1, led0=%b", led[0]); $finish; end
    sw = 16'h0001; #1
    if (led[0] !== 1'b0) begin $display("FAIL: design drives JA[0]=0, led0=%b", led[0]); $finish; end
    sw = 16'h0000; oe0 = 1; d0 = 1; #1
    if (led[0] !== 1'b1) begin $display("FAIL: released pin, tb drives 1, led0=%b", led[0]); $finish; end
    d0 = 0; #1
    if (led[0] !== 1'b0) begin $display("FAIL: released pin, tb drives 0, led0=%b", led[0]); $finish; end
    oe1 = 1; d1 = 1; #1
    if (led[1] !== 1'b1) begin $display("FAIL: JA[1] input, led1=%b", led[1]); $finish; end
    $display("PASS"); $finish;
  end
endmodule

previous: inout JA: JA[0] = oe ? d : 1'bz and read back; JA[7:1] = 'z, JA[1] read as input
next: the textbook's tristate buffer module (assign y = en ? a : 4'bz) instantiated four times, each driving one nibble of an output tri [15:0] port