SystemVerilog probes · 33Vivado: supported

inout JA: JA[0] = oe ? d : 1'bz and read back; JA[7:1] = 'z, JA[1] read as input

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.5 'Tristates' (p.86): 'Inferred Tristate buffers are implemented with ... An external pin of the circuit (OBUFT)'; UG953 v2022.2 Ch.5 IOBUF (p.386), a bidirectional buffer to an external pin: 'Design Entry Method ... Inference: Recommended'

What does the open-source chain do with it?

the Makefile drops a constant-z driver of an inout pin from the elaborated design (top.il, between yosys' elaboration and synthesis), so JA[1] is read like the read-only inout of 33b: the netlist passes the testbench (PASS) and the equivalence run ('EQV PASS'); 'pnr ok: 1 LUT, 0 FF'. yosys' 'Yosys has only limited support for tri-state logic at the moment.' warning stays

What is the probe's code?

From test/sv/33_tristate_pmod.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led, inout wire [7:0] JA);
  assign JA[0] = sw[0] ? sw[1] : 1'bz;   // drive the Pmod pin only when sw[0]
  assign JA[7:1] = 7'bz;
  assign led[0] = JA[0];
  assign led[1] = JA[1];
  assign led[15:2] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  wire [7:0] JA; reg oe0 = 1'b0, d0 = 1'b0, oe1 = 1'b0, d1 = 1'b0;
  assign JA[0] = oe0 ? d0 : 1'bz;
  assign JA[1] = oe1 ? d1 : 1'bz;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led), .JA(JA));
  initial begin
    sw = 16'h0003; #1
    if (led[0] !== 1'b1) begin $display("FAIL: design drives JA[0]=1, led0=%b", led[0]); $finish; end
    sw = 16'h0001; #1
    if (led[0] !== 1'b0) begin $display("FAIL: design drives JA[0]=0, led0=%b", led[0]); $finish; end
    sw = 16'h0000; oe0 = 1; d0 = 1; #1
    if (led[0] !== 1'b1) begin $display("FAIL: released pin, tb drives 1, led0=%b", led[0]); $finish; end
    d0 = 0; #1
    if (led[0] !== 1'b0) begin $display("FAIL: released pin, tb drives 0, led0=%b", led[0]); $finish; end
    oe1 = 1; d1 = 1; #1
    if (led[1] !== 1'b1) begin $display("FAIL: JA[1] input, led1=%b", led[1]); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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