SystemVerilog probes · 63Vivado: unverified

a real localparam cast to int: localparam int INC = int'(STEP); (2.6 rounds to 3)

Vivado: unverified. The open-source chain: all four stages pass.

What does Vivado do with it?

Unverified. UG901 v2023.2 contradicts itself for a cast of a real: Ch.10 Table 27 (p.285) lists 'Cast operator: Supported' and 'Real, shortreal, and realtime data types: Supported', and 'Real Numbers' (p.273) says 'They can only be used as parameter values.', but the same table (p.286) lists 'Operators with real operands: Not Supported', and the guide itself calls the cast an operator. No Vivado log in the corpus

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 33 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/63_real_cast.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  localparam real STEP = 2.6;           // a real parameter
  localparam int INC = int'(STEP);      // cast to int: rounds to 3
  assign led = sw + INC;
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      if (!(led === 16'(sw + 16'd3))) begin $display("FAIL: int'(2.6) is 3 (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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