SystemVerilog probes · 63bVivado: unverified

a real literal in a localparam used in an expression: localparam MAX = 1e1; ... count == MAX - 1 (a lab writes 50e6)

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. UG901 v2023.2 contradicts itself for an operator on a real: Ch.10 Table 27 (p.285) lists 'Real, shortreal, and realtime data types: Supported', and 'Real Numbers' (p.273) says 'They can only be used as parameter values.', but the same table (p.286) lists 'Operators with real operands: Not Supported', and MAX - 1 applies one to a real parameter. No Vivado log in the corpus: none of its .sv or .v files writes a real literal in a parameter

What does the open-source chain do with it?

since #5: rtl PASS; synth fail on both readers, and how differs by machine: on this Mac yosys' own reader dies with a segmentation fault on the real literal in the localparam and the CLI reports it as [yosys-crashed] with the line and the known cause (a real value in a parameter); on CI's yosys build it refuses without crashing; yosys-slang refuses the real cast (Feature unimplemented). No bitstream either way, so the row quotes no machine-specific line.

Which error pages explain the messages?

• yosys-crashed: yosys died with a signal instead of an error message; a real literal in a parameter is the known cause, and the line that holds one is named.

What is the probe's code?

From test/sv/63b_real_localparam_expr.

design.sv

module top(input logic clk, input logic btnC, output logic [15:0] led);
  localparam MAX = 1e1;                   // a real literal, 10 (a lab writes 50e6 for one second)
  logic [3:0] count = '0;
  logic blink = 1'b0;
  always_ff @(posedge clk)
    if (btnC) begin count <= 0; blink <= 0; end
    else if (count == MAX - 1) begin count <= 0; blink <= ~blink; end
    else count <= count + 1;
  assign led = {15'd0, blink};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0;
  wire [15:0] led;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  top dut(.clk(clk), .btnC(btnC), .led(led));
  integer i;
  initial begin
    btnC = 1; tick; btnC = 0;
    // blink toggles on every 10th edge: edges 10, 20, 30, ...
    for (i = 1; i <= 60; i = i + 1) begin
      tick; #1
      if (led !== {15'd0, 1'((i / 10) % 2)}) begin $display("FAIL: after %0d edges led=%h", i, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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