SystemVerilog probes · 105cVivado: unverified
a 4-word LUT RAM read before any write (mem[0] on the first edge)
Vivado: unverified. The open-source chain: all four stages pass.
| stage | today |
|---|---|
| rtl, simulation | pass |
| synth, synthesis | pass |
| netlist, the netlist | pass |
| bit, the bitstream | pass |
What does Vivado do with it?
Unverified. UG901 v2023.2 does not say what Vivado does with a distributed RAM that has no initial value before its first write; the 0 is the INIT #34 writes and nextpnr programs
What does the open-source chain do with it?
every stage prints 'PASS': the rtl stage prints 'note [sim-starts-as-board]: 1 memory without a start value starts as the board does, not at x: mem at 0 (a LUT RAM).' and starts every x bit of the memory at 0, so the before-any-write check passes where before #35 it reported mem[0] reads xxxxxxxx (expected 0) while netlist and bit passed: a silent wrong; the netlist stage prints 'EQV PASS: 262144 output bits compared, all equal' and bit 'pnr ok: 16 LUT, 0 FF, no clocked paths, timing not applicable'
Which error pages explain the messages?
- sim-starts-as-board: Not an error: a register or a memory of the design has no start value, and the simulation starts it where the board starts it (the reset value; 0 without a reset; a LUT RAM word at 0) instead of x, so a case or an if that reads it before the first reset takes the same branch in the simulation and on the board.
What is the probe's code?
From test/sv/105c_memory_before_write.
design.sv
// a memory read before anything is written to it: the board's LUT RAM starts at 0
module top(input logic clk, input logic btnU, input logic [15:0] sw, output logic [15:0] led);
logic [7:0] mem [0:3];
always_ff @(posedge clk) if (btnU) mem[sw[1:0]] <= sw[15:8];
assign led = {8'd0, mem[sw[3:2]]};
endmoduletb.sv
// every word reads 0 before the first write, as on the board; then a write and a read back
module tb;
logic clk = 1'b0, btnU = 1'b0;
logic [15:0] sw = 16'h0000;
logic [15:0] led;
top dut(.clk(clk), .btnU(btnU), .sw(sw), .led(led));
task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
initial begin #200000 $display("FAIL: timeout"); $finish; end
integer i;
initial begin
#1;
for (i = 0; i < 4; i++) begin sw[3:2] = i; #1 if (led !== 16'h0000) begin $display("FAIL: before any write mem[%0d] reads %b, expected 0 (the board's LUT RAM starts at 0)", i, led[7:0]); $finish; end end
sw = 16'hA500; btnU = 1'b1; tick; btnU = 1'b0; sw[3:2] = 2'd0; #1
if (led !== 16'h00A5) begin $display("FAIL: mem[0] after the write reads %b, expected a5", led[7:0]); $finish; end
sw[3:2] = 2'd1; #1 if (led !== 16'h0000) begin $display("FAIL: mem[1] reads %b, expected 0", led[7:0]); $finish; end
$display("PASS"); $finish;
end
endmodule