SystemVerilog probes · 66Vivado: unverified

alias a = b; (two nets made one)

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. UG901 v2023.2 Ch.10 Table 27 (p.286) lists 'Aliases: Supported' and, in the same table, 'Net aliasing: Not Supported'; alias is how two nets become one, so the guide contradicts itself. UG901 v2022.2 Table 8-1 (p.288-289) the same. No Vivado log in the corpus

What does the open-source chain do with it?

iverilog and yosys: syntax error at alias (design.sv:3)

What is the probe's code?

From test/sv/66_alias.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  wire [3:0] a, b;
  alias a = b;                         // a and b are one net
  assign a = sw[3:0];
  assign led = {12'd0, b};
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 16; i = i + 1) begin
      sw = {12'h3c5, i[3:0]}; #1
      if (!(led === {12'd0, sw[3:0]})) begin $display("FAIL: b is a (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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