SystemVerilog probes · 23bVivado: supported

the same package with import pkg::*; at file level, using an imported typedef

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288) and Ch.10 'Packages' (p.284) as for 23; the guide does not say where the import stands

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 1 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/23b_package_file_import.

design.sv

package cs223_pkg;
  typedef enum logic [1:0] {A, B, C} mode_t;
  parameter int W = 4;
  localparam logic [W-1:0] MAGIC = 4'hA;
  function automatic logic [W-1:0] twice(input logic [W-1:0] x);
    twice = x << 1;
  endfunction
endpackage
import cs223_pkg::*;
module top(input logic [15:0] sw, output logic [15:0] led);
  mode_t m;
  assign m = mode_t'(sw[1:0]);
  assign led[3:0]   = twice(sw[7:4]);
  assign led[7:4]   = cs223_pkg::MAGIC;
  assign led[9:8]   = (m == B) ? 2'd3 : 2'd0;
  assign led[15:10] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h0031; #1
    if (!(led === 16'h03A6)) begin $display("FAIL: package type/param/function (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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