SystemVerilog probes · 105Vivado: supported

four 4-bit registers read before the first clock edge: a synchronous reset to 5, an asynchronous reset to 4'b1010, no reset, a declared start value (logic [3:0] d = 4'd9)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2022.2 Ch.4 p.79: 'FDRE: D flip-flop with Clock Enable and Synchronous Reset', 'FDSE: D flip-flop with Clock Enable and Synchronous Set'; 'To initialize the content of a Register at circuit power-up, specify a default value for the signal during declaration'. What Vivado programs for a register WITHOUT a start value is not in the guide; the start values this row states are nextpnr-xilinx's def_init (xilinx/fasm.cc), checked on the product's own FASM

What does the open-source chain do with it?

every stage prints 'PASS': the rtl stage prints 'note [sim-starts-as-board]: 3 registers without a start value start as the board does, not at x: a at 4'b0101 and b at 4'b1010 (their reset values), c at 0 (no reset).' and starts them there, so the before-the-first-edge check passes where before #35 it reported a=xxxx b=xxxx c=xxxx d=1001 (expected 0101 1010 0000 1001) while netlist and bit passed: a silent wrong; the netlist stage prints 'EQV PASS: 262144 output bits compared, all equal' and bit 'pnr ok: 27 LUT, 16 FF'

Which error pages explain the messages?

• sim-starts-as-board: Not an error: a register or a memory of the design has no start value, and the simulation starts it where the board starts it (the reset value; 0 without a reset; a LUT RAM word at 0) instead of x, so a case or an if that reads it before the first reset takes the same branch in the simulation and on the board.

What is the probe's code?

From test/sv/105_reset_value_start.

design.sv

// four registers read before the first clock edge: a sync reset to 5, an async reset to 4'b1010, no reset, a
// start value in the declaration. The board starts each at its reset value, at 0 without one, at the declared value
module top(input logic clk, input logic btnC, input logic btnU, input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] a;            // synchronous reset to 5: the board starts it at 5 (bits 0 and 2 are FDSE, 1 and 3 FDRE)
  logic [3:0] b;            // asynchronous reset to 4'b1010: starts at 4'b1010 (FDPE and FDCE)
  logic [3:0] c;            // no reset: starts at 0
  logic [3:0] d = 4'd9;     // a declared start value: starts at 9 in every tool
  always_ff @(posedge clk) if (btnC) a <= 4'd5; else a <= a + 1;
  always_ff @(posedge clk or posedge btnU) if (btnU) b <= 4'b1010; else b <= b - 1;
  always_ff @(posedge clk) c <= sw[3:0];
  always_ff @(posedge clk) if (btnC) d <= 0; else d <= d + 1;
  assign led = {a, b, c, d};
endmodule

tb.sv

// led before the first clock edge must be what the board shows: a=0101 b=1010 c=0000 d=1001; then the registers run
module tb;
  logic clk = 1'b0, btnC = 1'b0, btnU = 1'b0;
  logic [15:0] sw = 16'h0003;
  logic [15:0] led;
  top dut(.clk(clk), .btnC(btnC), .btnU(btnU), .sw(sw), .led(led));
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  initial begin
    #1 if (led !== 16'b0101_1010_0000_1001) begin $display("FAIL: before the first edge a=%b b=%b c=%b d=%b, expected 0101 1010 0000 1001 (the board's start: the reset value, 0 without a reset, the declared value)", led[15:12], led[11:8], led[7:4], led[3:0]); $finish; end
    tick;
    if (led !== 16'b0110_1001_0011_1010) begin $display("FAIL: after one edge a=%b b=%b c=%b d=%b, expected 0110 1001 0011 1010", led[15:12], led[11:8], led[7:4], led[3:0]); $finish; end
    btnC = 1'b1; btnU = 1'b1; tick; btnC = 1'b0; btnU = 1'b0;
    if (led !== 16'b0101_1010_0011_0000) begin $display("FAIL: after reset a=%b b=%b c=%b d=%b, expected 0101 1010 0011 0000", led[15:12], led[11:8], led[7:4], led[3:0]); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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next: a 3-state enum FSM with a synchronous reset and no start value, read at the first clock edge before any reset (the board starts in IDLE and moves to RUN)