SystemVerilog probes · 104bVivado: supported

a 1-bit register set by the reset button (FDSE, no start value) read by an if before its first reset, beside a 16-bit counter (FDRE)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2022.2 Ch.4 p.79: 'FDRE: D flip-flop with Clock Enable and Synchronous Reset', 'FDSE: D flip-flop with Clock Enable and Synchronous Set'; 'To initialize the content of a Register at circuit power-up, specify a default value for the signal during declaration'. What Vivado programs for a register WITHOUT a start value is not in the guide; the start values this row states are nextpnr-xilinx's def_init (xilinx/fasm.cc), checked on the product's own FASM

What does the open-source chain do with it?

every stage prints 'PASS': setundef -one -params on the FDSE and -zero on the FDRE give net.v one FDSE at INIT = 1 beside 16 FDRE at INIT = 0, the values nextpnr programs, so led is all on (armed) before the first edge in RTL, netlist and bitstream alike. Before #34 the netlist stage failed: the FDSE kept INIT x and the if on armed drove every led to x, so the testbench reported the before-the-first-edge check as a failure (expected all on, armed) while rtl, synth and bit passed: a silent wrong

What is the probe's code?

From test/sv/104b_sync_set_start_one.

design.sv

// a set register (FDSE) read before its first reset: the netlist starts a register without a start value as
// the bitstream does (FDSE at 1), where the RTL has x
module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  logic armed;                      // set by the reset button, cleared by sw[0]
  logic [15:0] cnt;
  always_ff @(posedge clk)
    if (btnC)       armed <= 1'b1;
    else if (sw[0]) armed <= 1'b0;
  always_ff @(posedge clk)
    if (btnC)       cnt <= '0;
    else if (!armed) cnt <= cnt + 16'd1;
  always_comb
    if (!armed) led = cnt;
    else        led = 16'hFFFF;
endmodule

tb.sv

// checks led before any clock edge: the RTL's x armed takes the else branch (all on), and so must the
// netlist, which starts the FDSE at 1 as the bitstream does (an INIT forced to 0 would print all off)
module tb;
  logic clk = 1'b0, btnC = 1'b0;
  logic [15:0] sw = 16'h0000;
  logic [15:0] led;
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  initial begin
    #1 if (led !== 16'hFFFF) begin $display("FAIL: before the first edge led=%b, expected all on (armed)", led); $finish; end
    btnC = 1'b1; tick; btnC = 1'b0;
    if (led !== 16'hFFFF) begin $display("FAIL: after reset led=%b", led); $finish; end
    sw[0] = 1'b1; tick; sw[0] = 1'b0;
    if (led !== 16'h0000) begin $display("FAIL: disarmed led=%b", led); $finish; end
    tick; tick;
    if (led !== 16'h0002) begin $display("FAIL: counting led=%b", led); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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