patch notes · #203 October
#20 · Located diagnostics while typing
Live checks mark source lines and list problems. Actual errors disable Run; warnings remain runnable. Each diagnostic has a non-clickable hint showing coming soon!. Header paths, missing includes and repeated messages now produce useful locations.
Independent review reproduced a valid design timing out behind 50 pending checks after 60 edits. Checks are now coalesced: the same probe posted 7 checks with at most 1 pending, and Run completed in 16 seconds. A check timeout now says the sources are unchecked, replaces the worker and leaves Run available to compile again. The old board path blocked valid Run; the old testbench path falsely said there were no problems. Both behaviors were corrected.
The reviewer's final source checks passed 24/0 and its UI suite 126/0. Root tightened an older check that accepted not running as valid recovery. Remaining limits: queue wait counts against the request timeout; a check timeout can interrupt a concurrent run; two identical missing-include names can locate the first include site. No network cold-start timing is claimed.
CI follow-up (3 October). A WebKit run completed the memory design but exceeded the old 45-second aggregate check at 46.2 seconds. That check mixed worker speed with queue depth. The regression now records actual worker requests and replies at the Run click, requires at most one preceding check and no new lint while Run is active, and keeps bounded completion plus a working circuit. Four injected small jobs demonstrate that the same count rejects a backlog. The control uses a small circuit, avoiding an unnecessary second large memory simulation. Derived timing assertions were rejected during independent review: the worker's compile counter excludes hardware validation, and inferred durations did not provide independent evidence. Product scheduling remains unchanged.
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Every SystemVerilog construct measured so far, next to what Vivado does: the probes, stage by stage