patch notes · #173 October

#17 · Browser compilation checks the design and clears failed runs

Yosys errors now open their source file at the reported line. Missing module errors point to the instance. Synthesizable $display calls are removed with an explanation; a failed compile clears old outputs and DONE while POWER stays on. Edits survive a reload even when Run was never pressed. All five original regressions passed in Chromium and WebKit (5/0 each).

The worker checks the hierarchy, uses the Yosys reader with a Slang fallback and checks hardware without SIM before accepting the simulation netlist. Guards for undefined names, multiple drivers, non-constant asynchronous loads and unsupported source constructs remain active; latches produce a warning. Source file extensions retain Verilog-2005 versus SystemVerilog semantics. Package/interface dependencies, hierarchical references, temporary-name collisions and Xilinx library read state were corrected during review.

Root found a wrong interface output (00Zz) that the earlier direct-Yosys test did not cover. Flattening the actual worker netlist without scope-info cells fixed the DigitalJS boundary. Three actual worker netlists now pass their original native testbenches and 576 DigitalJS output comparisons. The additional engine-isolation suite passed 16 checks, including file collisions, a unit-scope enum, a user module named INV and four guard controls.

The last compilation-decision audit covers 133 cases: 124 matching decisions, 7 native-accept/browser-reject cases, 2 reverse differences and 0 infrastructure errors. The remaining rejects are unnamed instances, inherited procedural port direction, BUFG, MMCM, internal tristate, a netlist-form module and a bitstream cast. The two reverse differences are separate interface/package source files that the native CLI source selector omits; their browser behavior was tested above. These counts do not establish corpus-wide behavioral equivalence or hardware timing.

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Every SystemVerilog construct measured so far, next to what Vivado does: the probes, stage by stage