patch notes · unreleased

Preserve vector indices in pin validation

A parameterized port of width one ([0:0]) was mistaken for a scalar, and ports such as [4:1] were renumbered from zero. Both were rejected before place-and-route even with correct XDC assignments. The checker now uses Yosys vector metadata and declared offsets, including ascending ranges. The student's HDL and pin assignments do not need to change.

Validation: 35 focused checks over seven real Yosys port shapes, including missing/commented pins, missing IOSTANDARD and duplicate pin assignments. The old checker fails this regression. Probes 96 and 96b pass pin validation and place-and-route; RTL simulation and netlist equivalence are checked, and their FASM is converted to bitstreams. The restricted execution environment blocks CLI simulation's /dev/fd redirection and the frame converter's default /dev/stdout; validation uses the same Makefile simulation target and an explicit frame output filename. Full CLI success, VS Code GUI and physical board behavior are not claimed for this candidate. No full suite or deployment was run.

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Every SystemVerilog construct measured so far, next to what Vivado does: the probes, stage by stage